A semiconductor integrated circuit (IC) has a large number of circuit devices with complex interconnections. The placement and interconnection of the components of the IC may be facilitated with an Electronic Design Automation (EDA) tool, which allows an enormous flexibility in design and optimization of the IC. EDA technologies typically run on an operating system in conjunction with a microprocessor-based computer system or other programmable control system.
As a part of the IC design, a clock distribution network or a clock tree has to be constructed. The clock distribution network may indicate how a global clock signal is distributed from one or more signal sources to the circuit devices that require a clock signal. The circuit devices that require the clock signal may be memory devices such as flip-flops. As the clock signal may have to be carried a large number of flip-flops distributed throughout the IC, a clock distribution network may consume a significant amount of power. Being a consumer of a significant amount of power, a clock distribution network may be a candidate for design optimization for improving the power efficiency of the IC. ICs that can operate drawing less power are highly desirable in view of the rising demand of “untethered” devices, such as smartphones and tablets. A more power efficient IC may give a better battery life without a corresponding reduction in the functionality.
The distribution of the clock signal to various flip-flops scattered throughout the IC may be facilitated by clock buffers, which may act as nodes in the clock distribution network. A clock buffer may function as a source of the clock signal to a local cluster of flip-flops. Conventionally, each flip-flop may be assigned to the nearest clock buffer using a “nearest neighbor” approach. However, the flip-flops may not be distributed evenly throughout the IC. Therefore, a clock buffer close to a cluster with a high density of flip-flops may have to drive a heavier load compared to a clock buffer close to a sparsely populated cluster. For example, a cluster of 1000 flip-flops may be closer to, and therefore assigned to, a first clock buffer; and a cluster of 20 flip-flops may be closer to, and therefore assigned to, a second clock buffer. The first clock buffer connected to a larger number of flip-flops may need more wiring, more sub-buffers, and/or other circuit components to guarantee that the clock signal reaches all 1000 flip-flops simultaneously or near-simultaneously. The additional circuit components and wiring may translate into higher power consumption by the IC. On the other hand, the second clock buffer driving the smaller cluster may have latent power, and thus more flip-flops could be connected to the second clock buffer without increasing the power required.
The nearest neighbor approach may also sometimes defeat the purpose of a power reduction technique called “clock-gating.” Clock-gating uses circuit devices, sometimes called clock-gaters wired between tapping-points and clusters of flip-flops. Under designer specified conditions, a clock-gater may not provide the clock signal received from the respective tapping-point to the cluster of flip-flops wired to the clock-gater. In other words, the clock-gater may turn off the respective cluster of flip-flops if the cluster is not required for certain operations. Such turning off allows the IC to save power that would have been consumed by the cluster had it not been “gated” from the clock signal. The conventional nearest neighbor approach may warrant that the cluster of flip-flops wired to the same clock-gater be broken. For example, a first set of flip-flops in the cluster may be closer to a first clock buffer and a second set may be closer to a second clock buffer. To accommodate for the nearest neighbor assignment, an identical clock-gater may have to be generated (or the clock-gater may have to be “cloned”) so that each of the first set and second set may be wired to identical clock-gaters. The cloning is required to maintain the integrity of the original design that has a clock-gater wired to each of the first and second sets. However, the clock-gaters themselves need a lot a power, and therefore, cloning the clock-gaters may increase the power consumption by the IC.
What is therefore needed is a system that can depart from conventional nearest neighbor approach to reduce the aforementioned imbalance in the assignment of flip-flops for designing a more power efficient IC. What is also needed is a system that can depart from the conventional nearest neighbor approach to minimize the number of cloned clock-gaters for designing a more power efficient IC. What is also needed is a system that can track the global distribution and connections of various circuit devices and determine when it is appropriate to depart from the nearest neighbor approach.